About the Author
Gerald Clark is a 1994 graduate of the University of California at San Diego (UCSD). Gerald holds an MSEE in Electronic Circuits and Systems, and a BS in Computer Engineering both from UCSD. Gerald is the author of several papers in the communications and electronics field and is well known for his work in the San Diego high technology industry, awarded several patents in the Free Space Optical Laser Communications field while serving as Vice President of Engineering, LightPointe Communications, Inc. Gerald’s career involved companies like Loral Telemetry and Instrumentation where he lead the final phase of the Globalstar Telemetry and Command modem designed for Qualcomm- used to command, monitor, and control 54 LEO Globalstar Constellation Satellites. While serving as VP Engineering at Tiernan Communications, Gerald and his small team of hardware and software engineers were credited with “Digitizing American Television”, having demonstrated the first live HDTV ABC Monday Night Football game on-air transmission from New York to San Diego using Tiernan Communications, Inc. HDTV 1080i/720p MPEG-2 Encoders.
During the years 1996-2002, working as a telecommunications executive, Gerald’s business travels took him to various parts of the world exposing him to a plethora of cultures which acted as a catalyst for his research into mankind's earliest technologies and accomplishments, including the cultures of Mesopotamia and the surrounding areas of Turkey, Egypt, Persia, and Iraq, eventually leading to the cuneiform-inscribed tablets left by the Sumerians.
Knowledge of the Anunnaki here on Earth, both in the ancient past their presence here and now, is being fully-disclosed around the world. My hope is that this book will help the billions of primitive workers, left to fend for themselves on a hostile planet, to find hope that following the great destruction underway, wrought by the warring gods of Light and Dark, a promised peace in the new age of Aquarius is dawning, actually already upon us.
During the years 1996-2002, working as a telecommunications executive, Gerald’s business travels took him to various parts of the world exposing him to a plethora of cultures which acted as a catalyst for his research into mankind's earliest technologies and accomplishments, including the cultures of Mesopotamia and the surrounding areas of Turkey, Egypt, Persia, and Iraq, eventually leading to the cuneiform-inscribed tablets left by the Sumerians.
Knowledge of the Anunnaki here on Earth, both in the ancient past their presence here and now, is being fully-disclosed around the world. My hope is that this book will help the billions of primitive workers, left to fend for themselves on a hostile planet, to find hope that following the great destruction underway, wrought by the warring gods of Light and Dark, a promised peace in the new age of Aquarius is dawning, actually already upon us.
GERALD R. CLARK
Email: [email protected]
EDUCATION:
MS, Electrical Engineering, Electronic Circuits and Systems, University of California San Diego, Magna Cum Laude, 1998. Completed as part of PhD work, Evolvable Hardware.
BS, Computer Engineering, Revelle College, Department of Electrical and Computer Engineering, University of California at San Diego, Sum Cum Laude, 1994.
SKILL SUMMARY:
EXPERIENCE:
Principal Engineer, Hardy Process Solutions, 9440 Carrol Drive, San Diego, CA. Dec 2011-May 2013
Responsible for all phases of electronic hardware design, from market requirements to production delivery. Primary design responsibility for Hardy Products HI2080, HI6300, HI6310, HI6500, HI6510, HI6600 products. Recent skills as Principal Engineer include but are not limited to the following:
Authored Specifications, High and Low level Hardware Design and Test documentation for various circuit card assemblies. Completed Verilog 2005 FPGA Design using Lattice Diamond 1.4 and Active-HDL 9.1/Modelsim Simulator. FIR Filter design, simulation and implementation using RAM, ROM, MAC XP2 IP Express generated modules. Full TCL scripting for chip-level Verilog testbench coverage. Analog to Digital interface using SPI for AD7190. Resolved difficult space, timing, and power constraint issues for a miniature Weigh scale module that plugs into a PLC OEM’ed by a large industry-leading partner.
Ported and implemented Dallas Semiconductor 1-Wire Master in Verilog for Lattice XP2-17 FPGA. Developed 1-wire Master/Slave models in Verilog for DS2502. Developed custom microprocessor state-machine interface to drive the ds1wm.v model. This is a stand-alone Verilog 1-Wire Master that does not need a Microprocessor support. Implemented the ROM search algorithm for up to 10 64-bit devices, to include de-interleaving and discrepancy list management in Verilog HDL.
Hardware design experience at Hardy includes Galvanic isolation and hazardous area design principles and practices involving power supply design using the LT3574 Flyback Converter along with 1:1 transformer integration and simulation using LTSpice. Various primary to secondary transformer ratios specified for AC and DC systems. Buck and Boost regulator design experience to include the LT3970, LT1761, and the LP3990, and the Micrel 3291 TFT backlight booster to name a few. Skills include prototyping circuits, doing efficiency testing and full power analysis prior to regulator selection.
STM Cortex M4 Arm Microprocessor circuit card design with USB, RS232, RS485, and Ethernet. Utilized FSMC built-in bus to drive an integrated 4.3” TFT using and 8080 Microprocessor Interface for the Solomon Systech 1963 RGB driver, along with adjustable backlight control. Electronic schematic design using Orcad Capture: main controller board and the display board as part of a new product line at Hardy. EZ8 power supply re-design and schematic Rev B. Analog summing Junction board designs involving MOSFETs, Relays, and 1-Wire parasitic interfaces. Commonly use Schottkey, Zener, and Transient Suppression Diodes in industrial designs for Class 1, Div 2 Hazardous location, and FM. Experienced with ground plane isolation, bridging, and noise suppression techniques.
Senior Development Engineer, University of California, San Diego: CalIT2, March 2009-April 2010
Worked with faculty and staff developers and student researchers to define and execute projects in conjunction with the Computer Science and Engineering Department's embedded systems group and the California Institute for Telecommunications and Information Technology (CalIT2). As a Sr. Development Engineer and project lead, design activities were focused on the development of an ASIC netlist in excess of 2.5 million gates with FPGA prototyping prior to chip fabrication.
The multi-processor Neuronal Project was successfully mapped to a Xilinx Virtex-5 FPGA on a 12-layer custom printed circuit board, with no cuts and jumps the first fabrication cycle, on time and within budget.
Project Lead Responsibilities (10%):
Specific design responsibilities:
Senior Systems Analyst, Talon Communications Q1 2007
Responsibilities included authoring the functional specification and technical documentation, completing the electrical schematic for the circuit card design of an MPEG-4 AVC encoder for a MIL-SPEC application. Technical challenges included a two-state heating/cooling system (sans fans) using complex thermoelectric cooling materials within a sealed chamber. The high-speed SMPTE 292M input along with other electrical interfaces, were magnetically and optically isolated for signal integrity optimization. KLV Metadata insertion and extraction were used to synchronize timing between video from various locations. All PES and TS headers and fields were managed in accordance with appropriate adopted industry standards. Central to the design was an FPGA-based solution with embedded/flexible cores for the microprocessor, the HDRX front-end logic using a built-in serial to parallel converter at 1.4GHz input rate. The unit could be field upgraded via a web-based interface using a combination of programmable flash banks and DDRII RAM.
Senior Technical Consultant, Sanko Holding: 2000-2006
Perform various consulting services and research and analysis in telecommunications sector for international client, Sanko Holding, Bursa Inegol, Turkey. As a board consultant to Sanko, identify and model paradigm shifts in market segments that represent high growth. Once modeled, analyzed, and approved, the programs and or products are used to serve the 225 Million Turkish-speaking peoples in several countries in Europe and Asia. Authored patent # 20020131130 on behalf of Sanko Holding, recently awarded in an international filing to protect telecommunication market interests in the Turkish deregulated telecommunications market.
Rolf Del Mar, Nationally Certified HHP # 0505,
Health Care Practitioner (HHP) Business permit obtained in Del Mar, California June, 2005. Imaging equipment, analysis software, and various components of business established.
Guild for Structural Integration Certification Program Sept 2003-Nov 2004 Phase 1: Anatomy, Physiology, and Kinesiology: Boulder Colorado Sept 1-26, 2003
Phase 1: Anatomy, Physiology, and Kinesiology: Boulder Colorado Sept 1-26, 2003
Jeff Linn and Andy Goodwin, Instructors
Phase 2: Auditor Phase, Kauai HI: Sept. 27-Nov 20 2003
Emmett Hutchins, Instructor
Phase 2 Deliverable: Submit graduation paper prior to Phase 3
“Structure is Function and Energy”
Phase 3: Practitioner Training, Kauai HI, Sept-Nov, 2004
2 clients through 10-series, Emmett Hutchins, Nilce Silvera Instructors
Vice President Engineering, LightPointe, August 2000 – December 2002.
LightPointe designs and manufactures carrier-class optical transmission equipment using free-space optical (FSO) technology that delivers high-speed communications solutions to service providers. Responsibilities included leading a team of 40 worldwide engineers in the development and advancements of free-space optical products and microwave radio products for the ISM band and networking products. Worked closely with sales and marketing executives in defining corporate direction and developing relationships with telecommunications carriers like Qwest, MCI, Sprint, and the likes.
University of California, San Diego, Department of Electrical Engineering Aug 1993--Aug 1994
As an employee of UCSD engineering department, researched, prototyped, and presented research on a customer-funded multi-carrier spread spectrum secure communications system. Designed, prototyped, and modeled the adaptive multi-carrier spread spectrum communication system using mini-circuits functional elements (RF mixers, splitters, attenuators) and Labview for scope and simulation needs. PhD work continued under faculty advisor Dr. Paul Chau, Evolvable Hardware, with a completed prototype of the adaptive cellular array architecture FPGA. University research towards a PhD in Electrical engineering, having completed the academic coursework required for the PhD, while on sabattical from Tiernan Communications as Director of Hardware Engineering.
Vice President Engineering, Tiernan Communications, Dec 1996 – August 2000
Responsible for approximately 30 hardware and software development personnel in three separate markets: digital video broadcast, common carriers, and the Internet. Products developed for the broadcast included both standard and high definition digital television CODECs. The common carrier market was addressed using ATM and NMS equipment and software. Tiernan provided IP over DVB and data casting equipment for the Internet market.
As Director, Hardware Engineering for Tiernan, managed 25 junior & senior hardware engineers in the development of digital compression and decompression equipment for the commercial television broadcast market. As lead project engineer, developed multiple products and managed development teams from conception to manufacturing of final products. Technical duties were 80% while managerial duties were 20%.
While at Tiernan as a Senior Engineer, designed and implemented various video processing elements to include interpolation, decimation, and poly-phase filters. Algorithms were mapped to very large, flexible FPGAs as part of an MPEG-2 compression board. Developed various signal processing solutions for audio, video presentation and transport streams. VLSI Engineering Manager responsible for establishing the development platforms for high volume commercial ASICs, submitting product ideas, staffing and managing funded projects.
Involved in all aspects of PCB design including schematic capture, programmable logic, placement, routing, fabrication, debug, and customer technical support. Schematic capture using Valid/Cadence graphical editors. Control logic development and modeling using Altera MaxPlusII and Cadence Design Systems.
Sr. Design Engineer, Lockheed Martin Telemetry and Instrumentation, Feb. 1995 - Jan 1997
Responsible for full PCB design for very high speed commercial and space based telecommunication applications. Schematic-capture and hardware modeling using VHDL, AHDL, and Verilog. Developed synchronous state machines, asynchronous receivers, control logic and re-sampling filters using both schematic and with HDL based methods. Altera 7000 and FLEX 10K devices used. Designed using Xilinx XC400E/L parts for digital designs. Designed and implemented various algorithms to include an N-Ary PSK Modulator, Cholesky matrix inversion, USART, asynchronous microprocessor interface, polyphase filters, and spectral processing functions. Designed and implemented an evolvable hardware algorithm in the Altera Apex 20K system on a chip.
Completed PCB board simulations and signal conditioning experience. Experienced with amplifiers, sensor interfaces and electro-mechanical device interfaces, through-hole and surface mount devices. FCC design methodology experience obtained for both class A and B products. Analog transmission line and clock skew analysis and modeling experience using LineSim. Various IBS models developed and used in simulation to optimize selection of discrete components to reduce clock skew and transmission line coupling and reflection.RF noise and signal conditioning experience compliant with FCC standards.
Project lead for DSP MODEM and RF up and down converter PCBs operating at 2.2 GHz for the Globalstar commercial satellite constellation. Developed the modulator, demodulator, bit synchronizer, and frame synchronizer for the MODEM using ANALOG Devices ADSP 2181 assembly and code.
Served as technical liaison at Lockheed Martin responsible for focusing research on SATCOM product development. Involved in all aspects of the design, development, testing, and integration of the DSP and RF boards from both a hardware and software perspective.
Lead engineer responsible for Reed Solomon Channel Encoding and Decoding chip designed, modeled, and fabricated. Implemented programmable logic, DSP chip sets. Various modification made to the sequential algorithms for improved performance.
Systems Engineer, Reticular Systems Inc., Aug. 1989 - Feb. 1995
RSI was focused on using the Rotorcraft Pilot skills obtained in actual military service to create an expert system rule-base as part of a larger funding program under the Rotorcraft Pilot’s Associate program administered by DARPA. Created a rule-base expert system and codified it in the C-Language Integrated Production System, (CLIPS), an artificial intelligence rule-based modeling language. This effort lead to an expert system microprocessor design that was based on the concept of parallel rules firing simultaneously in hardware that triggered the microprocessor fetch cycle. Designed and implemented a custom application specific integrated circuit (ASIC) using Mentor Graphics chip design software on a Sparc 20 workstation. Very high speed hardware description language (VHDL) was used to model the chip function and a laser programmable fabrication facility was identified to etch the first silicon.
Designed, implemented, tested, and documented hardware and software products. Authored proposals to various agencies and managed scheduled deliveries as project engineer. Skills acquired in CMOS VLSI and VHDL modeling, simulation, netlist synthesis and optimization, test vector generation, scan-chain insertion for JTAG 1193 test standards, technology mapping and optimization, layout and FPGA laser programmable chip fabrication.
Chief Warrant Officer, U.S. Army, Aviation Branch, Nov. 1982 – Aug. 1989
Pilot in command of AH1S Cobra Attack Helicopters and OH58 KIOWA A-C Observation Helicopters with approximately 1500 flight hours. Other duties included Night Vision & Instrumentation Trainer, and Master Fitness Trainer. Trained in secure military communications protocol to include meackoning, intrusion, jamming interference, and OPSEC. Trained extensively at the National Training Center, Bicycle Lake California. Multiple Integrated Laser Engagement Systems Training involving weapons systems modeling and transponder code tracking used to debrief pilots in the Starwars building where Tom Clancy garnered technical data for his best-selling novels. Duty locations/timelines follow:
1982-1983 Fort Rucker, Alabama: Army Helicopter Maintenance/Repair Training
1983-1884 128th Aviation Battalion, Chun Chon Korea
1984-1985 Fort Rucker, Alabama: Army Helicopter Flight Training Center
o AH-1 Cobra Qualification Training
o OH-58 Kiowa Transition Course
o OH-58 Aeroscout Nighthawk Training
1985-1987 Fort Riley, Kansas;
o 1/1 Attack Helicopter Battalion (AHB), Marshall Army Airfield:
Pilot In Command AH-1S Modified, Production, ECAS, 4 rotations NTC, Ft. Irwin, CA.
2 deployments approximately 1 month duration, Return of Forces to Germany (REFORGER)
1987-1989 Fort Riley, Kansas (outprocessing assignment)
o ¼ Air Cavalry, Marshall Army Airfield
o Pilot in Command OH-58 Kiowa helicopters with 1 rotation to NTC, Ft. Irwin, CA.
PATENTS:
20040120717: Extend Source Free-Space Optical Communication System
20020171896: Free-Space Optical Communication System Employing Wavelength Conversion
20020131130: Multi-Tenant Unit Optical Network
20020131130: Free-Space Optical Communications Network
20020131123: Terrestrial Optical Communication Network of Integrated Fiber and Free-Space which Requires no Electro-Optical Conversion
PUBLICATIONS:
Structure is Function and Energy, GSI, 2004.
Novel Evolvable Hardware Architectures within Modern FPGAs
CEC-99 Conference, Washington DC, 1999.
Digitizing American Television,
IMAPS-98 Conference, San Diego, CA 1998.
Dynamic Real-Time Constrained Evolvable Hardware
PhD. Preliminary Oral, University of California, San Diego, 1998.
Evolvable Hardware Control for Dynamic Reconfigurable and Adaptive Computing,
7th EP 1998 Conference, San Diego, CA, 1998.
Improved Concurrent Processing for Telemetry, International Telemetry Conference, San Diego, CA, 1996.
Enhanced Concurrent Processing for Improved Telemetry Performance, European Telemetry Conference, Garmisch, Germany, 1996.
Efficient Implementation for a VLSI Bi-directional Associative Memory, UCSD conference paper, 1995.
MEMBERSHIPS/Licenses:
EDUCATION:
MS, Electrical Engineering, Electronic Circuits and Systems, University of California San Diego, Magna Cum Laude, 1998. Completed as part of PhD work, Evolvable Hardware.
BS, Computer Engineering, Revelle College, Department of Electrical and Computer Engineering, University of California at San Diego, Sum Cum Laude, 1994.
SKILL SUMMARY:
- Seasoned Industry Professional operates with integrity and professionalism on every project.
- Design and construction of prototypes custom analog and digital electronics and optical detection and transmission hardware
- Design and hands-on construction of controls for precision motors, thermal sensors and TEC coolers, and mechanical systems, PLLs, electronic schematic design and layout.
- Custom schematic and board layout, FPGA design, firmware development, and testing.
- Programming control software for PLL, filtering, and signal processing, and electro-optical systems.
- Design and assembly of test fixtures, bus and interface protocols.
- Work closely with multidisciplinary teams in complex system development, Verification, Validation, and transfer to manufacturing
- Contribute to corporate technology road map
- Lead the design, fabrication, integration, and functional testing of prototype subsystems developed in-house to include research, specification, and implementation.
- Ensure activities are consistent with project critical path, and respond appropriately to changing priorities. Manage activities and assigned projects to reach agreed objectives
- Work across the product development life-cycle from research phase breadboards, through functional prototypes, and into production.
- Excellent documentation, written and verbal communication skills
EXPERIENCE:
Principal Engineer, Hardy Process Solutions, 9440 Carrol Drive, San Diego, CA. Dec 2011-May 2013
Responsible for all phases of electronic hardware design, from market requirements to production delivery. Primary design responsibility for Hardy Products HI2080, HI6300, HI6310, HI6500, HI6510, HI6600 products. Recent skills as Principal Engineer include but are not limited to the following:
Authored Specifications, High and Low level Hardware Design and Test documentation for various circuit card assemblies. Completed Verilog 2005 FPGA Design using Lattice Diamond 1.4 and Active-HDL 9.1/Modelsim Simulator. FIR Filter design, simulation and implementation using RAM, ROM, MAC XP2 IP Express generated modules. Full TCL scripting for chip-level Verilog testbench coverage. Analog to Digital interface using SPI for AD7190. Resolved difficult space, timing, and power constraint issues for a miniature Weigh scale module that plugs into a PLC OEM’ed by a large industry-leading partner.
Ported and implemented Dallas Semiconductor 1-Wire Master in Verilog for Lattice XP2-17 FPGA. Developed 1-wire Master/Slave models in Verilog for DS2502. Developed custom microprocessor state-machine interface to drive the ds1wm.v model. This is a stand-alone Verilog 1-Wire Master that does not need a Microprocessor support. Implemented the ROM search algorithm for up to 10 64-bit devices, to include de-interleaving and discrepancy list management in Verilog HDL.
Hardware design experience at Hardy includes Galvanic isolation and hazardous area design principles and practices involving power supply design using the LT3574 Flyback Converter along with 1:1 transformer integration and simulation using LTSpice. Various primary to secondary transformer ratios specified for AC and DC systems. Buck and Boost regulator design experience to include the LT3970, LT1761, and the LP3990, and the Micrel 3291 TFT backlight booster to name a few. Skills include prototyping circuits, doing efficiency testing and full power analysis prior to regulator selection.
STM Cortex M4 Arm Microprocessor circuit card design with USB, RS232, RS485, and Ethernet. Utilized FSMC built-in bus to drive an integrated 4.3” TFT using and 8080 Microprocessor Interface for the Solomon Systech 1963 RGB driver, along with adjustable backlight control. Electronic schematic design using Orcad Capture: main controller board and the display board as part of a new product line at Hardy. EZ8 power supply re-design and schematic Rev B. Analog summing Junction board designs involving MOSFETs, Relays, and 1-Wire parasitic interfaces. Commonly use Schottkey, Zener, and Transient Suppression Diodes in industrial designs for Class 1, Div 2 Hazardous location, and FM. Experienced with ground plane isolation, bridging, and noise suppression techniques.
Senior Development Engineer, University of California, San Diego: CalIT2, March 2009-April 2010
Worked with faculty and staff developers and student researchers to define and execute projects in conjunction with the Computer Science and Engineering Department's embedded systems group and the California Institute for Telecommunications and Information Technology (CalIT2). As a Sr. Development Engineer and project lead, design activities were focused on the development of an ASIC netlist in excess of 2.5 million gates with FPGA prototyping prior to chip fabrication.
The multi-processor Neuronal Project was successfully mapped to a Xilinx Virtex-5 FPGA on a 12-layer custom printed circuit board, with no cuts and jumps the first fabrication cycle, on time and within budget.
Project Lead Responsibilities (10%):
- Detailed task planning and budgeting.
- Weekly team meetings, design reviews, and quarterly detailed progress reports.
- Managed graduate students and other senior developers that contributed to the very large ASIC design.
Specific design responsibilities:
- Capturing and translating customer requirements into system level requirements documents.
- Authored functional specifications high and low level detailed design documents.
- Managed code control server (SVN) and all purchasing and equipment needs for project.
- Performed System-level simulations using SystemC.
- Documented, commented, authored, synthesized, simulated and debugged structural and RTL code using both VHDL and Verilog.
- Wrote test benches for each model, performed static and constrained timing analysis.
- Designed interfaces for SRAM, FLASH, DDRII, PROM loaders, and wrote PCIe drivers.
- Utilized IP core in the SOC design.
Senior Systems Analyst, Talon Communications Q1 2007
Responsibilities included authoring the functional specification and technical documentation, completing the electrical schematic for the circuit card design of an MPEG-4 AVC encoder for a MIL-SPEC application. Technical challenges included a two-state heating/cooling system (sans fans) using complex thermoelectric cooling materials within a sealed chamber. The high-speed SMPTE 292M input along with other electrical interfaces, were magnetically and optically isolated for signal integrity optimization. KLV Metadata insertion and extraction were used to synchronize timing between video from various locations. All PES and TS headers and fields were managed in accordance with appropriate adopted industry standards. Central to the design was an FPGA-based solution with embedded/flexible cores for the microprocessor, the HDRX front-end logic using a built-in serial to parallel converter at 1.4GHz input rate. The unit could be field upgraded via a web-based interface using a combination of programmable flash banks and DDRII RAM.
Senior Technical Consultant, Sanko Holding: 2000-2006
Perform various consulting services and research and analysis in telecommunications sector for international client, Sanko Holding, Bursa Inegol, Turkey. As a board consultant to Sanko, identify and model paradigm shifts in market segments that represent high growth. Once modeled, analyzed, and approved, the programs and or products are used to serve the 225 Million Turkish-speaking peoples in several countries in Europe and Asia. Authored patent # 20020131130 on behalf of Sanko Holding, recently awarded in an international filing to protect telecommunication market interests in the Turkish deregulated telecommunications market.
Rolf Del Mar, Nationally Certified HHP # 0505,
Health Care Practitioner (HHP) Business permit obtained in Del Mar, California June, 2005. Imaging equipment, analysis software, and various components of business established.
Guild for Structural Integration Certification Program Sept 2003-Nov 2004 Phase 1: Anatomy, Physiology, and Kinesiology: Boulder Colorado Sept 1-26, 2003
Phase 1: Anatomy, Physiology, and Kinesiology: Boulder Colorado Sept 1-26, 2003
Jeff Linn and Andy Goodwin, Instructors
Phase 2: Auditor Phase, Kauai HI: Sept. 27-Nov 20 2003
Emmett Hutchins, Instructor
Phase 2 Deliverable: Submit graduation paper prior to Phase 3
“Structure is Function and Energy”
Phase 3: Practitioner Training, Kauai HI, Sept-Nov, 2004
2 clients through 10-series, Emmett Hutchins, Nilce Silvera Instructors
Vice President Engineering, LightPointe, August 2000 – December 2002.
LightPointe designs and manufactures carrier-class optical transmission equipment using free-space optical (FSO) technology that delivers high-speed communications solutions to service providers. Responsibilities included leading a team of 40 worldwide engineers in the development and advancements of free-space optical products and microwave radio products for the ISM band and networking products. Worked closely with sales and marketing executives in defining corporate direction and developing relationships with telecommunications carriers like Qwest, MCI, Sprint, and the likes.
- Network architecture secure design & redundancy using FSO
- Patent on dynamic secure infrared wavelength translation
- Patent on multi-tenant unit wireless optical network distributed architecture (secure optical data distribution)
- Patent on all optical networks requiring no electro-optical conversion for IT and Network architectures.
- Secure, point-to-point Class 1M, 3B infrared laser communication equipment, design, test and manufacture
University of California, San Diego, Department of Electrical Engineering Aug 1993--Aug 1994
As an employee of UCSD engineering department, researched, prototyped, and presented research on a customer-funded multi-carrier spread spectrum secure communications system. Designed, prototyped, and modeled the adaptive multi-carrier spread spectrum communication system using mini-circuits functional elements (RF mixers, splitters, attenuators) and Labview for scope and simulation needs. PhD work continued under faculty advisor Dr. Paul Chau, Evolvable Hardware, with a completed prototype of the adaptive cellular array architecture FPGA. University research towards a PhD in Electrical engineering, having completed the academic coursework required for the PhD, while on sabattical from Tiernan Communications as Director of Hardware Engineering.
Vice President Engineering, Tiernan Communications, Dec 1996 – August 2000
Responsible for approximately 30 hardware and software development personnel in three separate markets: digital video broadcast, common carriers, and the Internet. Products developed for the broadcast included both standard and high definition digital television CODECs. The common carrier market was addressed using ATM and NMS equipment and software. Tiernan provided IP over DVB and data casting equipment for the Internet market.
As Director, Hardware Engineering for Tiernan, managed 25 junior & senior hardware engineers in the development of digital compression and decompression equipment for the commercial television broadcast market. As lead project engineer, developed multiple products and managed development teams from conception to manufacturing of final products. Technical duties were 80% while managerial duties were 20%.
While at Tiernan as a Senior Engineer, designed and implemented various video processing elements to include interpolation, decimation, and poly-phase filters. Algorithms were mapped to very large, flexible FPGAs as part of an MPEG-2 compression board. Developed various signal processing solutions for audio, video presentation and transport streams. VLSI Engineering Manager responsible for establishing the development platforms for high volume commercial ASICs, submitting product ideas, staffing and managing funded projects.
Involved in all aspects of PCB design including schematic capture, programmable logic, placement, routing, fabrication, debug, and customer technical support. Schematic capture using Valid/Cadence graphical editors. Control logic development and modeling using Altera MaxPlusII and Cadence Design Systems.
Sr. Design Engineer, Lockheed Martin Telemetry and Instrumentation, Feb. 1995 - Jan 1997
Responsible for full PCB design for very high speed commercial and space based telecommunication applications. Schematic-capture and hardware modeling using VHDL, AHDL, and Verilog. Developed synchronous state machines, asynchronous receivers, control logic and re-sampling filters using both schematic and with HDL based methods. Altera 7000 and FLEX 10K devices used. Designed using Xilinx XC400E/L parts for digital designs. Designed and implemented various algorithms to include an N-Ary PSK Modulator, Cholesky matrix inversion, USART, asynchronous microprocessor interface, polyphase filters, and spectral processing functions. Designed and implemented an evolvable hardware algorithm in the Altera Apex 20K system on a chip.
Completed PCB board simulations and signal conditioning experience. Experienced with amplifiers, sensor interfaces and electro-mechanical device interfaces, through-hole and surface mount devices. FCC design methodology experience obtained for both class A and B products. Analog transmission line and clock skew analysis and modeling experience using LineSim. Various IBS models developed and used in simulation to optimize selection of discrete components to reduce clock skew and transmission line coupling and reflection.RF noise and signal conditioning experience compliant with FCC standards.
Project lead for DSP MODEM and RF up and down converter PCBs operating at 2.2 GHz for the Globalstar commercial satellite constellation. Developed the modulator, demodulator, bit synchronizer, and frame synchronizer for the MODEM using ANALOG Devices ADSP 2181 assembly and code.
Served as technical liaison at Lockheed Martin responsible for focusing research on SATCOM product development. Involved in all aspects of the design, development, testing, and integration of the DSP and RF boards from both a hardware and software perspective.
Lead engineer responsible for Reed Solomon Channel Encoding and Decoding chip designed, modeled, and fabricated. Implemented programmable logic, DSP chip sets. Various modification made to the sequential algorithms for improved performance.
Systems Engineer, Reticular Systems Inc., Aug. 1989 - Feb. 1995
RSI was focused on using the Rotorcraft Pilot skills obtained in actual military service to create an expert system rule-base as part of a larger funding program under the Rotorcraft Pilot’s Associate program administered by DARPA. Created a rule-base expert system and codified it in the C-Language Integrated Production System, (CLIPS), an artificial intelligence rule-based modeling language. This effort lead to an expert system microprocessor design that was based on the concept of parallel rules firing simultaneously in hardware that triggered the microprocessor fetch cycle. Designed and implemented a custom application specific integrated circuit (ASIC) using Mentor Graphics chip design software on a Sparc 20 workstation. Very high speed hardware description language (VHDL) was used to model the chip function and a laser programmable fabrication facility was identified to etch the first silicon.
Designed, implemented, tested, and documented hardware and software products. Authored proposals to various agencies and managed scheduled deliveries as project engineer. Skills acquired in CMOS VLSI and VHDL modeling, simulation, netlist synthesis and optimization, test vector generation, scan-chain insertion for JTAG 1193 test standards, technology mapping and optimization, layout and FPGA laser programmable chip fabrication.
Chief Warrant Officer, U.S. Army, Aviation Branch, Nov. 1982 – Aug. 1989
Pilot in command of AH1S Cobra Attack Helicopters and OH58 KIOWA A-C Observation Helicopters with approximately 1500 flight hours. Other duties included Night Vision & Instrumentation Trainer, and Master Fitness Trainer. Trained in secure military communications protocol to include meackoning, intrusion, jamming interference, and OPSEC. Trained extensively at the National Training Center, Bicycle Lake California. Multiple Integrated Laser Engagement Systems Training involving weapons systems modeling and transponder code tracking used to debrief pilots in the Starwars building where Tom Clancy garnered technical data for his best-selling novels. Duty locations/timelines follow:
1982-1983 Fort Rucker, Alabama: Army Helicopter Maintenance/Repair Training
1983-1884 128th Aviation Battalion, Chun Chon Korea
1984-1985 Fort Rucker, Alabama: Army Helicopter Flight Training Center
o AH-1 Cobra Qualification Training
o OH-58 Kiowa Transition Course
o OH-58 Aeroscout Nighthawk Training
1985-1987 Fort Riley, Kansas;
o 1/1 Attack Helicopter Battalion (AHB), Marshall Army Airfield:
Pilot In Command AH-1S Modified, Production, ECAS, 4 rotations NTC, Ft. Irwin, CA.
2 deployments approximately 1 month duration, Return of Forces to Germany (REFORGER)
1987-1989 Fort Riley, Kansas (outprocessing assignment)
o ¼ Air Cavalry, Marshall Army Airfield
o Pilot in Command OH-58 Kiowa helicopters with 1 rotation to NTC, Ft. Irwin, CA.
PATENTS:
20040120717: Extend Source Free-Space Optical Communication System
20020171896: Free-Space Optical Communication System Employing Wavelength Conversion
20020131130: Multi-Tenant Unit Optical Network
20020131130: Free-Space Optical Communications Network
20020131123: Terrestrial Optical Communication Network of Integrated Fiber and Free-Space which Requires no Electro-Optical Conversion
PUBLICATIONS:
Structure is Function and Energy, GSI, 2004.
Novel Evolvable Hardware Architectures within Modern FPGAs
CEC-99 Conference, Washington DC, 1999.
Digitizing American Television,
IMAPS-98 Conference, San Diego, CA 1998.
Dynamic Real-Time Constrained Evolvable Hardware
PhD. Preliminary Oral, University of California, San Diego, 1998.
Evolvable Hardware Control for Dynamic Reconfigurable and Adaptive Computing,
7th EP 1998 Conference, San Diego, CA, 1998.
Improved Concurrent Processing for Telemetry, International Telemetry Conference, San Diego, CA, 1996.
Enhanced Concurrent Processing for Improved Telemetry Performance, European Telemetry Conference, Garmisch, Germany, 1996.
Efficient Implementation for a VLSI Bi-directional Associative Memory, UCSD conference paper, 1995.
MEMBERSHIPS/Licenses:
- IEEE
- Optical Society San Diego
- Optical Society of America (OSA)
- Society of Photonics and Industrial Engineers (SPIE)
- Association of Bodywork and Massage Professionals: ABMP
- American Taekwondo Association : (ATA) Little Rock, AR, Rec. Black Belt
- Guild for Structural Integration: GSI, Boulder CO.
- National Certification for Therapeutic Massage and Bodywork Professionals
- Commercial Rotary Wing Instrument License
- Private Airplane, Single Engine Land, Instrument Ticket
- United States Hang Gliding Association (USHGA) Hang III
Gerald's Autobiography
Living My Personal Legend: & A Love That Lives On
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Nearly all of us a have a dream inside of us burning to be fulfilled. We either do what it takes to make it come true or we continue living life, dreaming about it. This book holds the story of a many who fulfilled his dream, not once, not twice but over and over again. A man without fear and with a passion for living. Starting from humble roots where one could choose to stay, Gerald chose to rise up in multiple scenarios living and fulfilling not just one dream, but multiple dreams.
This is the autobiography of best-selling Author, Gerald R. Clark who wrote “The Anunnaki of Nibiru” “The 7th Planet, Mercury Rising” and his screen-play “Odyssey Ki.” Gerald fulfilled his dream to fly becoming a helicopter pilot and Chief Warrant Officer II in the US Army, rising against the odds various times to make it so. From the Army he went to college and become a successful Electrical Engineer where he met his first wife and became a father to three beautiful children. He didn’t stop there and went for more training and become a healthcare practitioner in the art of Structural Integration, also known is Rolfing, opening his own practice helping others heal. After a rough divorce he was later led to meet his soul mate where he went on to become a best-selling author writing two books, a screenplay, becoming a well known speaker doing interviews, podcasts, and opening 7th Planet Broadcasting. He taught himself how to animate, wrote and produced The Anunnaki Series working with other like minded souls, and a movie script "Odyssey Ki". He then went on to open his own online school with his wife, Gravity Body Academy and held hands-on training. From his first breath to his last breath Gerald Clark lived an inspirational life. His autobiography is filled with gems to illuminate your path so you can do the same. Gerald shows us that we don't have to live the status quo, and we don't necessarily have to pursue only one path, we can follow our hearts calling and live our own personal legend!
This book is not only an autobiography but also has the love story of Gerald and Christa Clark written by his soul mate Christa. A first hand look into their success, trials, tribulations, love for one another and her devastating loss. A widows tale of her own true love filled with insights on how to live your BEST life and keep living even after life throws you a hard curve ball, and to never stop believing that true love, a healthy, pure and inspirational love can exist for you.
Quoted from the book:
"Once upon a time, a girl met a man, and he helped her blossom into the woman she is today. Two souls destined to meet, to share their path, love, knowledge and with the world. Without his fire her smooth waters wouldn’t have created the waves of change that were required."
"I learned while life can be hard, scary and at times full of changes and the unknown. Remember, you have the courage to face it, you’ll make it through to the other side, pass through that finish line, pass through the gate, survive, then hopefully thrive." - Christa Clark
"What is interesting is that a person, place, or thing has the potential to change our fated path and become our destiny. Pay attention to what you are paying attention to. Discover why it is interesting to you, for good or bad and then choose wisely. These are the fated forks in the road along our stopping points of life."
"You are a cosmic seed from the spawn of the INFINITE SOURCE, the CREATOR OF ALL. The books I have written empower the primitive worker to take the reins of their destiny, activating their hidden ba energetic key that will lead one back to the LIGHT, which is our destined home beyond the Duot, in another dimension and locale, neighbors to the CIRCLE OF LIGHT. Live your dream in this simulator, then let’s meet back at the SOURCE frequency." - Gerald Clark